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LIS3L02DQ
INERTIAL SENSOR: 3Axis - 2g DIGITAL OUTPUT LINEAR ACCELEROMETER
PRELIMINARY DATA
1

FEATURES
2.7V TO 3.6V SINGLE SUPPLY OPERATION 1.8V COMPATIBLE IOs I2C/SPI DIGITAL OUTPUT INTERFACES MOTION ACTIVATED INTERRUPT SOURCE FACTORY TRIMMED DEVICE SENSITIVITY AND OFFSET EMBEDDED SELF TEST HIGH SHOCK SURVIVABILITY
Figure 1. Package
QFN-44
Table 1. Order Codes
Part Number LIS3L02DQ Package QFN-44
2
DESCRIPTION
the X, Y axis and Z axis. The device bandwidth may be selected accordingly to the application requirements. A self-test capability allows the user to check the functioning of the system. The device may be configured to generate an inertial wake-up/interrupt signal when a programmable acceleration threshold is exceeded along one of the three axis. The LIS3L02DQ is available in plastic SMD package and it is specified over a temperature range extending from -20C to +70C. The LIS3L02DQ belongs to a family of products suitable for a variety of applications: - Motion activated functions in mobile terminals - Antitheft systems and Inertial navigation - Gaming and Virtual Reality input devices - Vibration Monitoring and Compensation
The LIS3L02DQ is a tri-axis digital output linear accelerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an I2C/SPI serial interface. The sensing element, capable to detect the acceleration, is manufactured using a dedicated process called THELMA (Thick Epi-Poly Layer for Microactuators and Accelerometers) developed by ST to produce inertial sensors and actuators in silicon. The IC interface instead is manufactured using a CMOS process that allows high level of integration to design a dedicated circuit which is factory trimmed to better match the sensing element characteristics. The LIS3L02DQ is capable of measuring accelerations over a maximum bandwidth of 2.0 KHz for Figure 2. Block Diagram
S1X S1Y S1Z rot S2Z S2Y S2X MUX
CHARGE AMPLIFIER
DE MUX
Reconstruction Filter I2C CS SCL/SPC
Reconstruction Filter
Regs Array
SDA/SDIO SDO
SPI
Reconstruction Filter
VOLTAGE & CURRENT REFERENCE
TRIMMING CIRCUIT & TEST INTERFACE
CLOCK & PHASE GENERATOR
CONTROL LOGIC & INTERRUPT GEN.
RDY/INT
January 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 3 1/19
LIS3L02DQ
Table 2. Pin Description
N 1 to 2 3 4 5 to 12 13 14 15 16 17 Pin NC GND Vdd NC Reserved Reserved RDY/INT SDO SDA/ SDI/ SDO SCL/SPC CS Vdd_IO Vdd GND NC Internally not connected 0V supply Power supply Internally not connected Leave unconnected or connect to Vdd Leave unconnected or connect to GND Data ready/inertial wake-up interrupt SPI Serial Data Output I2C Serial Data (SDA) SPI Serial Data Input (SDI)8 3-wire Interface Serial Data Output (SDO) I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) Power supply for I/O pads Power supply 0V supply Internally not connected Function
18 19 20 21 22 23 to 44
Figure 3. Pin Connection (Top view)
NC NC NC NC NC NC NC NC NC NC NC
NC
NC NC NC NC NC
Z Y
NC GND Vdd NC NC NC
1
LIS3L02DQ
NC NC NC NC NC NC
X
NC NC NC NC
SDO
SCL/SPC
Reserved
Reserved
SDA/SDI/SDO
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RDY/INT
Vdd_IO
GND
NC
Vdd
CS
DIRECTION OF THE DETECTABLE ACCELERATIONS
LIS3L02DQ
Table 3. Electrical Characteristcs (Temperature range -20C to +70C) All the parameters are specified @ Vdd=3.3V and T=25C unless otherwise noted
Symbol Vdd Vdd_IO Idd IddPdn BW FS FSAcc So 0g-Offset NL Parameter Supply voltage I/O pads Supply voltage Supply current Current consumption in power-down mode Digital Filter Cut-Off frequency (-3dB) Measurement range2 Full-scale accuracy Device Resolution Zero g level Non Linearity T = 25C T = 25C BW=56Hz T = 25C Best fit straight line X, Y axis BW=56Hz Best fit straight line Z axis BW=56Hz DR1 DR2 DR3 DR4 Ton Output data rate Output data rate Output data rate Output data rate Turn-on time Dec factor = 128 Dec factor = 64 Dec factor = 32 Dec factor = 8 -50 1 1.8 T = 25C T = 25C 70 2.0 2.0 1 50 2.2 Test Condition Min. 2.7 1.8 1 Typ.1 Max. 3.6 Vdd+0.1 1.5 10 1150 Unit V V mA A Hz g g mg mg % FS
3
% FS
280 560 1120 4480 50
Hz Hz Hz Hz ms
Notes 1 Typical specifications are not guaranteed 2 Guaranteed by wafer level test and measurement of initial offset and sensitivity
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ABSOLUTE MAXIMUM RATING Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 4. Absolute Maximum Ratings
Symbol Vdd Vdd_IO Vin APOW AUNP TOP TSTG Supply voltage I/O pads Supply voltage Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO, SDO, RDY/INT) Acceleration (Any axis, Powered, Vdd=3.3V) Acceleration (Any axis, Unpowered) Operating Temperature Range Storage Temperature Range Ratings Maximum Value -0.3 to 6 -0.3 to Vdd +0.1 Vss -0.3 to Vdd +0.3 3000g for 0.5 ms 3000g for 0.5 ms -20 to +70 -40 to +105 C C Unit V V V
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3
FUNCTIONALITY
3.1 Sensing element The THELMA process is utilized to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and free to move on a plane parallel to the substrate itself. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase. The equivalent circuit for the sensing element is shown in the below figure; when a linear acceleration is applied, the proof mass displaces from its nominal position, causing an imbalance in the capacitive halfbridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. The nominal value of the capacitors, at steady state, is few pF and when an acceleration is applied the maximum variation of the capacitive load is few tenth of pF. Figure 4. Equivalent electrical circuit
Cps1 Rs1 S1x Cs1x
Cpr
Rr
Cs2x S2x Cps2 Cps1 Rs2 Rs1 S1y Cs1y
Cpr
Rr rot
Cs2y S2y Cps2 Rs2
Cps1
Rs1 S1z Cs1z
Cpr
Rr
Cs2z S2z Cps2 Rs2
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3.2 IC Interface The complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by three analog-to-digital converters, one for each axis, that translates the produced signal into a digital bitstream. The converters are tigthly coupled with dedicated reconstruction filters which removes the high frequency components of the quantization noise and provides low rate and high resolution digital words. The charge amplifier and the converters are operated respectively at 107.5 KHz and 35.8 KHz. The data rate at the output of the reconstruction depends on the user selected Decimation Factor (DF) and span from 280 Hz to 4.48 KHz. The acceleration data may be accessed through an I2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS3L02DQ features a Data-Ready signal (DRY) which indicated when a new set of measured acceleration data is available thus simplifying data synchronization in digital system employing the device itself. The LIS3L02DQ may also be configured to generate an inertial wake-up/interrupt signal when a programmable acceleration threshold is exceeded along one of the three axis. 3.3 Factory calibration The IC interface is factory calibrated to provide to the final user a device ready to operate. The parameters which are trimmed are: gain, offset, common mode and internal clock frequency. The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation thus allowing the final user to employ the device without any need for further calibration.
4
DIGITAL INTERFACES
The register embedded inside the LIS3L02DQ may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in SPI mode or in 3-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS line must be tied high (i.e connected to Vdd). Table 5. Serial Interface Pin Description
PIN Name CS PIN Description SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) SPI Serial Data Output (SDO)
SCL/SPC
SDA/SDI/SDO
SDO
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4.1 I2C Serial Interface The LIS3L02DQ I2C is a bus slave. The I2C is employed to write the data into the registers whose content can also be read back. The relevant I2C terminology is given in the table below Table 6. Serial Interface Pin Description
Term Transmitter Receiver Master Slave The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master Description
There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd through a pull-up resistor embedded inside the LIS3L02DQ. When the bus is free both the lines are high. 4.1.1 I2C Operation The transaction on the bus is started through a START signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The address can be made up of a programmable part and a fixed part, thus allowing more than one device of the same type to be connected to the I2C bus. The Slave ADdress (SAD) associated to the LIS3L02DQ is 0011101. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. The I2C embedded inside the LIS3L02DQ behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a salve address is sent, once a slave acknowledge has been returned, a 8-bit sub-address will be transmitted: the 7 LSB represent the actual register address while the MSB enables address autoincrement. If the MSB of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write. If the LSB of the slave address was `1' (read), a repeated START condition will have to be issued after the two sub-address bytes; if the LSB is `0' (write) the Master will transmit to the slave with direction unchanged. Transfer when Master is writing one byte to slave
Master Slave ST SAD + W SAK SUB SAK DATA SAK SP
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Transfer when Master is writing multiple bytes to slave:
Master Slave ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP
Transfer when Master is receiving (reading) one byte of data from slave:
Master Slave ST SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP
Transfer when Master is receiving (reading) multiple bytes of data from slave
Master Slave ST SAD + W SAK SUB SAK SR SAD + R SAK DATA MAK
Master Slave
SR DATA
MAK DATA
NMAK
SP
Data are transmitted in byte format. Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant Bit (MSB) first. If a receiver can't receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn't acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to read. 4.2 SPI Bus Interface The SPI interface present inside the LIS3L02DQ is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SPDI and SPDO. 4.2.1 Read & Write registers Figure 5. Read & write protocol
CS
SPC
SPDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SPDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
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CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SPDI and SPDO are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the Read Register and Write Register commands are completed in 16 clocks pulses. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15) starts at the last falling edge of SPC just before the rising edge of CS. - bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SPDO at the start of bit 8. - bit 1-7: address AD(6:0). This is the address field of the indexed register. - bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). - bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). 4.2.2 SPI Read Figure 6. SPI Read protocol
CS
SPC
SPDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SPDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command consists is performed with 16 clocks pulses: - bit 0: READ bit. The value is 1. - bit 1-7: address AD(6:0). This is the address field of the indexed register. - bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). 4.2.3 SPI Write Figure 7. SPI Write protocol
CS
SPC
SPDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
The SPI Write command consists is performed with 16 clocks pulses. - bit 0: WRITE bit. The value is 0. - bit 1-7: address AD(3:0). This is the address field of the indexed register. - bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first).
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4.2.4 SPI Read in 3-wires mode 3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in A_IF_CTRL2. Figure 8. SPI Read protocol in 3-wires model
CS
SPC
SPDI/O RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command consists is performed with 16 clocks pulses: - bit 0: READ bit. The value is 1. - bit 1-7: address AD(6:0). This is the address field of the indexed register. - bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
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5
REGISTERS MAPPING
The table given below provides a listing of the registers embedded in the device and the related address. All the "application related" registers (i.e. control, status, data) are mapped into Bank2 so to simplify their access when running through the SPI interface.
Register Address Reg. Name Type Binary 0000000 - 0010101 OFFSET_X OFFSET_Y OFFSET_Z GAIN_X GAIN_Y GAIN_Z rw rw rw rw rw rw 0010110 0010111 0011000 0011001 0011010 0011011 0011100 - 0011111 CTRL_REG1 CTRL_REG2 rw rw 0100000 0100001 0100010 WAKE_UP_CFG WAKE_UP_SRC WAKE_UP_ACK rw r r 0100011 0100100 0100101 0100110 STATUS_REG OUTX_L OUTX_H OUTY_L OUTY_H OUTZ_L OUTZ_H THS_L THS_H rw r r r r r r rw rw 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 - 1111111 Hex 00 - 15 16 17 18 19 1A 1B 1C - 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 - 3F 8 8 8 8 8 8 8 8 8 Reserved 8 8 8 Reserved 8 8 Reserved 8 8 8 8 8 8
Size (Bit)
Comment Reserved Loaded at boot Loaded at boot Loaded at boot Loaded at boot Loaded at boot Loaded at boot Reserved
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6
REGISTERS DESCRIPTION
The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. 6.1 OFFSET_X (16h)
OX7 OX6 OX5 OX4 OX3 OX2 OX1 OX0
OX7, OX0
Digital Offset Trimming for X-Axis
6.2 OFFSET_Y (17h)
OY7 OY6 OY5 OY4 OY3 OY2 OY1 OY0
DOY7, DOY0
Digital Offset Trimming for Y-Axis
6.3 OFFSET_Z (18h)
OZ7 OZ6 OZ5 OZ4 OZ3 OZ2 OZ1 OZ0
OZ7, OZ0
Digital Offset Trimming for Z-Axis
6.4 GAIN_X (19h)
GX7 GX6 GX5 GX4 GX3 GX2 GX1 GX0
GX7, GX0
Digital Gain Trimming for X-Axis
6.5 GAIN_Y (1Ah)
GY7 GY6 GY5 GY4 GY3 GY2 GY1 GY0
GY7, GY0
Digital Gain Trimming for Y-Axis
6.6 GAIN_Z (1Bh)
GZ7 GZ6 GZ5 GZ4 GZ3 GZ2 GZ1 GZ0
GZ7, GZ0
Digital Gain Trimming for Z-Axis
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6.7 CTRL_REG1 (20h)
PD1 PD0 DF1 DF0 ST Zen Yen Xen
PD1, PD0
Power Down Control (00: power-down mode; 01: device on) Decimation Factor Control (00: decimate by 128; 01: decimate by 64; 10: decimate by 32; 11: decimate by 8) Self Test Enable (0: normal mode; 1: self-test active) Z-axis enable (0: axis off; 1: axis on) Y-axis enable (0: axis off; 1: axis on) X-axis enable (0: axis off; 1: axis on)
DF1, DF0
ST
Zen
Yen
Xen
6.8 CTRL_REG2 (21h)
Res BDU BLE BOOT IEN DRDY SIM DAS
Res BDU
Reserved Block Data Update (0: continuous update; 1: output registers not updated until MSB and LSB reading) Big/Little Endian selection (0: little endian; 1: big endian) Reboot memory content Interrupt ENable (0: data ready on RDY pad; 1: int req on RDY pad) Enable Data-Ready generation SPI Serial Interface Mode selection (0: 4-wire interface; 1: 3-wire interface) Data Alignment Selection (0: 12 bit right justified; 1: 16 bit left justified)
BLE
BOOT IEN
DRDY SIM
DAS
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6.9 WAKE_UP_CFG (23h)
AOI LIR MZH MZL MYH MYL MXH MXL
AOI
And/Or combination of Interrupt events (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch interrupt request (1: interrupt request latched) Mask Z High Interrupt (1: enable int req on measured accel. value higher than preset threshold) Mask Z Low Interrupt (1: enable int req on measured accel. value lower than preset threshold) Mask Y High Interrupt (1: enable int req on measured accel. value higher than preset threshold) Mask Y Low Interrupt (1: enable int req on measured accel. value lower than preset threshold) Mask X High Interrupt (1: enable int req on measured accel. value higher than preset threshold) Mask X Low Interrupt (1: enable int req on measured accel. value lower than preset threshold)
LIR
MZH
MZL
MYH
MYL
MXH
MXL
6.10 WAKE_UP_SOURCE (24h)
x IA ZH ZL YH YL XH XL
IA MZH MZL MYH MYL MXH MXL
Interrupt Active Z High Z Low Y High Y Low X High X Low
6.11 WAKE_UP_ACK (25h) Reading at this address resets the WAKE_UP_SOURCE register.
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6.12 A_STATUS_REG (27h)
ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA
ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA
X, Y and Z axis Data Overrun Z axis Data Overrun Y axis Data Overrun Y axis Data Overrun X, Y and Z axis new Data Available Z axis new Data Available Y axis new Data Available X axis new Data Available
6.13 OUTX_L (28h)
XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0
XD7, XD0
X axis acceleration data LSb
6.14 OUTX_H (29h)
When reading the register in "12 bit right justified" mode the most significant bits (7:4) are replaced with bit 3 (i.e. XD15XD12=XD11, XD11, XD11, XD11).
XD15
XD14
XD13
XD12
XD11
XD10
XD9
XD8
XD15, XD8
X axis acceleration data MSb
6.15 OUTY_L (2Ah)
YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0
YD7, YD0
Y axis acceleration data LSb
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6.16 OUTY_H (2Bh)
When reading the register in "12 bit right justified" mode the most significant bits (7:4) are replaced with bit 3 (i.e. YD15YD12=YD11, YD11, YD11, YD11).
YD15
YD14
YD13
YD12
YD11
YD10
YD9
YD8
YD15, YD8
Y axis acceleration data MSb
6.17 OUTZ_L (2Ch)
ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0
ZD7, ZD0
Z axis acceleration data LSb
6.18 OUTZ_H (2Dh)
When reading the register in "12 bit right justified" mode the most significant bits (7:4) are replaced with bit 3 (i.e. ZD15ZD12=ZD11, ZD11, ZD11, ZD11).
ZD15
ZD14
ZD13
ZD12
ZD11
ZD10
ZD9
ZD8
ZD15, ZD8
Z axis acceleration data MSb
6.19 THS_L (2Eh)
THS7 THS6 THS5 THS4 THS3 THS2 THS1 THS0
THS7, THS0
Inertial Wake Up Acceleration Threshold Lsb
6.20 THS_H (2Fh)
THS15 THS14 THS13 THS12 THS11 THS10 THS9 THS8
THS15, THS8
Inertial Wake Up Acceleration Threshold Msb
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7
PACKAGE INFORMATION
Figure 9. QFN-44 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 b D E e J K L P 5.04 5.04 0.38 0.48 45 REF 1.70 0.19 0.20 0.25 7.0 7.0 0.50 5.24 5.24 0.58 0.198 0.198 0.015 0.019 45 REF TYP. 1.80 MAX. 1.90 0.21 0.30 MIN. 0.067 0.007 0.008 0.01 0.276 0.276 0.020 0.206 0.206 0.023 TYP. 0.071 MAX. 0.075 0.008 0.012 inch
OUTLINE AND MECHANICAL DATA
QFN-44 (7x7x1.8mm) Quad Flat Package No lead
M
G
M
N
34 44 44 1
33
1
DETAIL "N"
23 11
22
12
DETAIL G
SEATING PLANE
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8
REVISION HISTORY
Table 7. Revision History
Date February 2004 12 January, 2005 Revision 1 2 First Issue Changed the Operating Temperature range: from -40C to +85C to -20C to +70C. Changed some datas on the Table 3 Electrical Characteristics. Changed the section 6.8 CTRL_REG2 (21h). The title in first page has been changed as the following: INERTIAL SENSOR: 3Axis - 2g DIGITAL OUTPUT LINEAR ACCELEROMETER Description of Changes
20 January, 2005
3
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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